`timescale 1ns / 1ns
// Description: Clock and reset system
// Author: JerryTech
// License: GPLv3

module clock_tree(
    input   wire fpga_clk,

    output  wire usb_clk,
    output  wire usb_resetn,

    output  wire audio_clk,
    output  wire audio_resetn

);

wire       clk72mhz;
wire       aud_clk;
reg        clk_locked;

usb_rPLL u_usb_pll (
    .clkout     ( usb_clk   ), 
    .clkin      ( fpga_clk  ),
    .lock       ( usb_resetn )
);

audio_master_rPLL your_instance_name(
    .clkout     ( clk72mhz  ), //output clkout
    .lock       (           ),
    .clkin      ( usb_clk   ) //input clkin
);

audio_rPLL aud_pll(
    .clkout     (               ), //output clkout
    .clkoutd    ( audio_clk     ), //output clkoutd
    .lock       ( audio_resetn  ), //output lock
    .clkin      ( clk72mhz      ) //input clkin
);



endmodule

